The present invention relates to an electronic circuit latch capable to latching data at its output by assuming more than one stable state.
The simplest form of latch is a flip flop logic circuit which is a binary cell capable of storing one bit of information. Such circuits are constructed from NAND gates and NOR gates and can be a simple flip flop having a set and reset input. The input signals to the latch can be controlled by applying them through AND circuits each having a clock input so that the flip flop can change state only when a clock pulse occurs. Alternatively, data can be fed through a two input AND gate coupled to one input of an OR circuit. The passage of the data through the OR gate is controlled by a latch circuit which has the output of the OR gate as one input and a clock signal as another. Such circuits can either be level sensitive, that is, able to pass data any time during an enabling clock period and then latch the data transmitted or edge triggered in which the state of the input is passed to the output at the leading edge of the enable clock pulse and then latched. For applications in which the exact time of arrival of the data may be uncertain but is within a given time interval, a level sensitive latch is appropriate. Where it is desired to transmit the data at a given instant of time coincident with other events, an edge triggered latch is appropriate. As VLSI technology moves towards smaller and smaller layouts and corresponding faster speeds clearly it is desirable to develop latches which minimize transmittal delays.
A second limitation of conventional latches arises due to there being no provision for the circuit designer to monitor the latched signal prior to its transmission to another circuit. Consequently, it is often difficult to know about the integrity of a latched signal before it is transmitted on for further processing.